CPE 273

Hierarchical Digital Design Methodology

Advanced logic modeling, simulation, and synthesis techniques. Topics include modeling, simulation, and synthesis techniques, using Hardware Description Language (HDL's), Register Transfer Level (RTL) representation, high level functional partitioning, functional verification and testing, computer-aided logic synthesis, logical verification and testing, timing and delay analysis, automated place and route process', and design with Application Specific Integrated Circuits (ASICs) and programmable logic.

Units: 3.0